The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, to a dicing (scribing) technique for separating or dividing a semiconductor wafer into chips (or pellets).
In the field of manufacture of semiconductor devices, CMP (Chemical Mechanical Polishing) has conventionally been known as a technique of flattening the surface of a film. The CMP has an advantage particularly in smoothening and flattening the surface of a film widely; however, it has the following problem. When an insulation film is formed in order to fill a recess portion and all the insulation film except that in a recess portion is removed by the CMP, the surface of the insulation film can be flattened in accordance with the depth of the recess portion if the width of the recess portion is small. If, however, the width of the recess portion is large (e.g., 1.5 μm or more), the insulation film in the recess portion is cut too much and a film reduction phenomenon called dishing occurs.
FIG. 1 illustrates a semiconductor memory device to explain a prior art countermeasure against the dishing.
The semiconductor memory device is usually obtained by dividing a semiconductor wafer 101 into a plurality of semiconductor chips 102 and separating the chips along a dicing line 103.
A TEG (Test Element Group) is generally provided on the dicing line 103. It is therefore unfavorable that the flatness of an insulation film be degraded by dishing even on the dicing line 103.
As one method for remedying the dishing on the dicing line 103, it can be thought that a laminated film 104 is formed on the major surface (within a so-called dicing region) of the semiconductor wafer 101, corresponding to the dicing line 103.
More specifically, in the semiconductor chip, a first insulation film (e.g., an SiO2 film) 111 is buried in the major surface portion of the semiconductor wafer 101 corresponding to the dicing line 103, to form an element isolation region 112 having an STI (Shallow Trench Isolation) structure, and then a gate electrode portion 113 of a selective transistor serving as a word line is formed on the major surface of the wafer 101 corresponding to the semiconductor chip 102.
The gate electrode portion 113 is constituted as follows. A polysilicon film 115 having a thickness of about 1000 Å is formed on a gate oxide film 114 and a Wsi film (tungsten silicide film) 116 having a thickness of about 500 Å is formed on the polysilicon film 115 to produce a pattern. Moreover, a SiN film (silicon nitride film) 117 having a thickness of about 2000 Å is formed as a cap member on the Wsi film 116.
At the same time when the gate electrode portion 113 is formed, the laminated film 104 of the gate oxide film 114, polysilicon film 115, WSi film 116 and SiN film 117 is formed on the first insulation film 111.
A diffusion layer 118 serving as a source or a drain is formed on the major surface portion of the semiconductor wafer 101, which is adjacent to the gate electrode portion 113, and then a second insulation film (e.g., SiO2 film) 119 is deposited on the entire surface of the resultant structure. The surface of the second insulation film 119 is flattened by CMP so as to have a thickness of approximately 5000 Å on the laminated film 104. An opening portion 120 communicating with the diffusion layer 118 is formed in the second insulation film 119.
After that, a W (tungsten) film having a thickness of about 2500 Å is deposited on the second insulation film 119 so as to fill the opening portion 120 and then patterned to form a bit line 121 and a diffusion layer contact portion 122 integrally with each other as one component.
A third insulation film (e.g., SiO2 film) 123 is deposited on the whole surface of the resultant structure and then the surface of the film 123 is flattened by CMP using the top surface of the bit line 121 as a stopper.
A fourth insulation film (e.g., SiO2 film) 124 is deposited on the entire surface of the third insulation film 123, and the surface of the film 124 is flattened by CMP so as to have a thickness of approximately 5000 Å. Then, an opening portion 125 communicating with the bit line 121 is formed in the fourth insulation film 124.
The opening portion 125 is filled with the W film to form a bit line contact portion 126 communicating with the bit line 121, and a fifth insulation film (e.g., SiO2 film) 127 is deposited on the whole surface of the resultant structure. The surface of the fifth insulation film 127 is flattened by CMP so as to have a thickness of about 3000 Å on the bit line contact portion 126.
A wiring groove 128 communicating with the bit line contact portion 126 is formed in the fifth insulation film 127 and filled with an Al/Cu (aluminum/copper) film to form a wiring layer (first metal layer) 129 serving as a fuse layer.
A sixth insulation film (e.g., SiO2 film) 130 having a thickness of 3000 Å or more is deposited on the entire surface of the resultant structure and its surface is flattened by CMP. Then, an opening portion 131 communicating with the wiring layer 129 is formed in the sixth insulation film 130.
Thereafter, a seventh insulation film (e.g., TEOS=Tetra Ethoxy Silane film) 132, an eighth insulation film (e.g., SiN film) 133, and a passivation film (e.g., PI film=polyimide film) 134 are deposited in order on the entire surface of the resultant structure. An opening portion 135 connecting with the opening portion 131, is formed in the passivation film 134, eighth insulation film 133, seventh insulation film 132 and sixth insulation film 130 by RIE (Reactive Ion Etching).
Simultaneously, parts of the passivation film 134, eighth insulation film 133, seventh insulation film 132 and sixth insulation film 130 are removed by RIE to form the dicing line 103.
In this case, the sixth insulation film 130 is etched, with a thickness of at least 3000 Å left, such that the total thickness of the insulation films 119, 123, 124, 127 and 130 on the laminated layer 104 is 18500 Å.
Part of each of the opening portions 131 and 135 is filled with the Al/Cu film to form a power supply wiring layer (second metal layer) 136 and concurrently a plurality of chips 102.
After that, the semiconductor wafer 101 is diced along the dicing line 103 and cut into the chips (pellets) 102 by a cut portion 137 and, in other words, a plurality of semiconductor memory device can be obtained at once.
In a semiconductor memory device so obtained, the laminated film 104 is provided on the major surface of the semiconductor wafer 101 corresponding to the dicing line 103. It is thus possible to prevent dishing when the surface of the third insulation film 123 is flattened by CMP.
The bit line 121, diffusion layer contact portion 122, bit line contact portion 126 and wiring layers 129 and 136 also serve as a crack stopper. Thus, even though a crack occurs at the time of dicing, it can be prevented from reaching the semiconductor chip 102.
Although the laminated film 104 remedies dishing on the dicing line 103, stress is easy to concentrate on the insulation film on the dicing line 103 at the time of dicing, thus causing a problem in which a crack 138 easily occurs in the insulation film formed on the dicing line 103. The occurrence of the crack on the dicing line 103 is not so serious. If, however, the insulation film on the dicing line 103 is chipped and dropped due to the crack 138 caused on the insulation film, the chipped film becomes a crack waste and then a pollution source in the subsequent process. If, in particular, the crack waste is large and moves onto the semiconductor chip 102, its influence becomes more serious.
If all the insulation film on the dicing line 103 is eliminated before dicing, the crack 138 can be prevented from occurring. In this case, however, the dicing line 103 cannot be formed concurrently with formation of the opening portion 135, thus complicating the manufacturing process.